Generally, the goals of integrated circuit (IC) chip design are to optimize total power consumption, IC device density, timing and various other parameters (e.g., electrical parameters) in order to develop products that meet desired performance specifications at a relatively low-cost and within a relatively fast turn-around time. IC chip design typically begins with a high-level description of the IC. This high-level description sets out the requirements for the IC chip and is stored on a data storage device in, for example, a hardware description language (HDL), such as VHDL or Verilog. A logic synthesis tool can synthesize the high-level description into low-level constructs. For example, in the case of application-specific integrated circuit (ASIC) design the high-level description can be synthesized into a gate-level netlist using library elements (e.g., standard cells in standard cell ASIC design or gate array base cells in gate array ASIC design). After logic synthesis, a placement tool can establish placement (i.e., location on the IC chip) of the library elements. Then, a routing tool can perform routing and, more particularly, can define the wires that will interconnect the library elements. Following routing, a timing analysis tool can perform a timing analysis. For example, a static timing analysis (STA) tool can be used to predict the performance of an IC chip and to verify that the IC chip will function correctly. That is, STA can be used to predict the arrival times of clock and data signals and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit, as designed, will function properly with a sufficiently high probability. Logic synthesis, placement, routing, and timing can be iteratively repeated, as necessary, to generate the final IC design. Since the final IC design is based on the results of a timing analysis, it is imperative that the timing analysis be as accurate as possible.